FD_ENA=Val_0x0, CKEN=Val_0x0, CLK_SEL=Val_0x0, CKDIV=Val_0x0
CANFD Control Register
| CKDIV | CANFD functional clock divisor n: Clock divided by n 0 (Val_0x0): Illegal values 1 (Val_0x1): Illegal values 2 (Val_0x2): Clock divided by 2 3 (Val_0x3): Clock divided by 3 |
| CKEN | CANFD clocks enable 0 (Val_0x0): Disable 1 (Val_0x1): Enable |
| CLK_SEL | CANFD functional clock source select 0 (Val_0x0): Select 38.4 MHz oscillator clock (HFOSC_CLK) 1 (Val_0x1): Select 160 MHz PLL clock (160M_CLK) |
| FD_ENA | CANFD FD-mode enable 0 (Val_0x0): Disable FD-mode 1 (Val_0x1): Enable FD-mode |